1. Field of the Invention
The present invention relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, a method for manufacturing a solid-state imaging element, and a semiconductor device. In particular, the present invention relates to a solid-state imaging device in which a plurality of semiconductor substrates are layered, a method for manufacturing the solid-state imaging device, a method for manufacturing a solid-state imaging element in which a plurality of semiconductor substrates are layered, and a semiconductor device.
2. Description of the Related Art
Commonly, in manufacturing of a semiconductor chip, after a plurality of semiconductor chips are formed on a wafer, the wafer is diced with a blade along a scribe line provided around the semiconductor chips so as to divide the wafer into individual semiconductor chips.
For suppressing chipping occurring in the dicing with a blade, such a structure is proposed that a chipping prevention wall (guard ring) for suppressing progression of film peeling in dicing is formed inside a wiring layer which is positioned in the scribe line.
In recent years, a three-dimensional mounting technique by which a plurality of semiconductor substrates are bonded to each other has been generally employed. Japanese Unexamined Patent Application Publication No. 2008-182142 proposes a back-illuminated type solid-state imaging device in which a semiconductor substrate is bonded to a support substrate. Further, a semiconductor device in which semiconductor wafers are bonded to each other and are connected to each other by a through electrode is also proposed.